1. Field of the Invention
The present invention relates to a memory testing apparatus for testing a memory such as, for example, a memory formed by a semiconductor integrated circuit, and more particularly, to such memory testing apparatus provided with means for displaying on a display means locations or addresses of failure memory cells of a memory under test on the basis of the test results.
2. Description of the Related Art
FIG. 4 shows in block diagram a configuration of a conventional memory testing apparatus having a failure data display apparatus added to the memory testing apparatus. In FIG. 4, a reference character MIN denotes a main frame in which the memory testing apparatus is housed, a reference character TSH denotes a test head of the memory testing apparatus, and a reference character WST denotes a controller constructed by a workstation for controlling the entire operation of the main frame MIN.
The memory testing apparatus within the main frame MIN comprises, generally, a pattern generator 11, a logical comparator 12, a failure memory 13 for storing failure data of a memory under test, and a control unit 14. The control unit 14 operates in response to control instructions from the controller WST to control the entire operation of the main frame MIN.
That is, the pattern generator 11 generates a test pattern signal corresponding to a specified type of memory, an address signal, and control signals to apply the test pattern and the address signal, and a device control signal to a device under test DUT (a memory under test in this example) located on the test head TSH.
The test pattern signal is written, in accordance with the address signal and the device control signal having sent to the device under test DUT together with the test pattern signal, in one of the memory cells of the device under test DUT having an address specified by the address signal.
After the writing operation is completed, the pattern generator 11 generates an expected value pattern, an address signal, and a device control signal to input the expected value pattern to the logical comparator 12, where the expected value data is logically compared with the data read out of the device under test DUT. Every time the both data do not accord with each other, the logical comparator 12 generates a failure data having, for example, a logical high level H, which data is written in one memory cell having the same address of the failure memory 13 as that of the device under test DUT at which the failure has occurred.
After the completion of the test, the failure data stored in the failure memory 13 is read out therefrom to the controller WST to display the locations or addresses of the failure memory cells of the memory under test DUT on a display apparatus 21. Specifically, the controller WST has a control unit 22 for controlling the main frame MIN, and the control unit 22 reads the failure data out of the failure memory 13 through the control unit 14 provided in the main frame MIN. The failure data read out of the failure memory 13 is supplied to the controller WST where the locations of the failure memory cells are mapped and displayed on the two-dimensional screen of the display apparatus 21. The display apparatus 21 performs the operations for displaying the failure information as well as for saving the failure information as image data.
FIG. 5 shows a display screen for displaying thereon the failure information. Each section (block) shown in FIG. 5 represents one memory cell of the memory. In FIG. 5, each section indicated by slant lines represents a failure memory cell. Each section is displayed by one dot of the display screen of the display apparatus 21. This image data is stored in an image memory so that the image data can be read out thereof and displayed at any time.
As mentioned above, in the prior art memory testing apparatus, since the failure data is displayed using the controller (workstation) WST for controlling the operation of the main frame MIN, there is a disadvantage that the next testing cannot be performed during the time duration that the controller WST is operating to display the failure data. FIG. 6 shows the time sequence of the prior art memory testing apparatus. As is clear from FIG. 6, each time a test period of a device ends, a failure data display period DSP necessarily succeeds thereto. Specifically, when a test period TEST of a device A ends, the process goes to a failure data display period DSP of the device A during which the test for a next device B cannot be started. As a result, after the failure data display period DSP of the device A has completed, the test for the next device B is started as shown in FIG. 6. Accordingly, there is a drawback in the prior art memory testing apparatus that the test period T of each device becomes long, resulting in low efficiency of the test.